1. Field of the Invention
The present invention relates to a semiconductor memory device, a memory controller, and a data processing system including these, and more particularly relates to a semiconductor memory device that requires holding of data by a refresh operation, a memory controller that controls the semiconductor memory device, and a data processing system including the semiconductor memory device and the memory controller.
2. Description of Related Art
A DRAM (Dynamic Random Access Memory) as one of representative semiconductor memory devices has a memory cell constituted by one transistor and one capacitor. Therefore, an area occupied per one memory cell is small, and the DRAM has excellent characteristics such that a high integration can be obtained. On the other hand, because data written in the memory cell is lost after a predetermined time, it is necessary to periodically perform a refresh operation.
In the refresh operation, many sense amplifiers are simultaneously activated, and therefore a relatively large current flows. By taking this point into consideration, Japanese Patent Application Laid-open No. 2000-30439 proposes a method of suppressing a peak current by shifting a timing of performing a refresh operation in each bank when a refresh command is issued from outside. This method can be easily achieved by independently providing in each bank a transmission path of a refresh signal within a chip.
Meanwhile, in recent years, there has been proposed a method of configuring a semiconductor memory device by integrating a frontend portion and a backend portion of a DRAM in separate chips and by stacking these chips (Japanese Patent Application Laid-open No. 2007-157266). According to this method, plural core chips in each of which backend portions are integrated have an increased occupied area that can be allocated to a memory core. Therefore, the memory capacity per one chip (per one core chip) can be increased. Meanwhile, an interface chip that has frontend portions integrated therein and is common to plural core chips can be manufactured by a process that is different from a process of manufacturing the memory core. Accordingly, a circuit can be formed by high-speed transistors. Further, because plural core chips can be allocated to one interface chip, it is possible to provide a semiconductor memory device having a very large capacity and high speed as a whole.
In this type of semiconductor memory device, it is very important to manufacture core chips by the same mask to reduce the manufacturing cost.
However, when core chips are manufactured by the same mask, these core chips mutually have the same circuit configurations. Therefore, it becomes difficult to selectively send a signal to a specific core chip from an interface chip. Consequently, in this type of semiconductor memory device, it is difficult to selectively perform a refresh operation by providing plural transmission paths of a refresh signal as described in Japanese Patent Application Laid-open No. 2000-30439.